1. Field of the Invention
The present invention relates to semiconductor static and dynamic memory structures and more particularly, to a pipelined semiconductor memory chip divided into sub-arrays having globally and locally generated decoding and locally generated precharge signals.
2. Background Art
The present invention includes a number of particular techniques and structures which are related to general concepts found in the prior art. For example, the present invention employs a form of sub-array structure, uses multiplexed sense amplifiers and incorporates a precharge technique.
Representative prior art references which describe memories with sub-arrays, but not for pipelined operation, include
U.S. Pat. No. 4,569,036, issued Feb. 4, 1986 to Fujii et al, entitled SEMICONDUCTOR DYNAMIC MEMORY DEVICE;
U.S. Pat. No. 4,554,646, issued Nov. 19, 1985 to Yoshimoto et al, entitled SEMICONDUCTOR MEMORY DEVICE;
U.S. Pat. No. 4,542,486, issued Sept. 17, 1985 to Anami et al, entitled SEMICONDUCTOR MEMORY DEVICE;
U.S. Pat. No. 4,482,984, issued Nov. 13, 1984 to Oritani, entitled STATIC TYPE SEMICONDUCTOR MEMORY DEVICE;
U.S. Pat. No. 4,447,895, issued May 8, 1984 to Asano et al, entitled SEMICONDUCTOR MEMORY DEVICE;
U.S. Pat. No. 4,384,347, issued May 17, 1983 to Nakano, entitled SEMICONDUCTOR MEMORY DEVICE;
U.S. Pat. No. 4,222,112, issued Sept. 9, 1980 to Clemons et al, entitled DYNAMIC RAM ORGANIZATION FOR REDUCING PEAK CURRENT.
References in the prior art directed to multiplexed sense amplifier input techniques include
U.S. Pat. No. 4,511,997, issued Apr. 16, 1985 to Nozaki et al, entitled SEMICONDUCTOR MEMORY DEVICE;
U.S. Pat. No. 4,509,148, issued Apr. 2, 1985 to Asano et al, entitled SEMICONDUCTOR MEMORY DEVICE;
U.S. Pat. No. 4,477,739, issued Oct. 16, 1984 to Proebsting et al, entitled MOSFET RANDOM ACCESS MEMORY CHIP;
U.S. Pat. No. 4,447,893, issued May 8, 1984 to Murakami, entitied SEMICONDUCTOR READ ONLY MEMORY DEVICE;
U.S. Pat. No. 4,410,964, issued Oct. 18, 1983 to Nordling et al, entitled MEMORY DEVICE HAVING A PLURALITY OF OUTPUT PORTS.
Descriptions of techniques using precharge signals cependent upon a memory address are found in U.S. Pat. No. 4,520,465, issued May 28, 1985 to Sood, entitled METHOD AND APPARATUS FOR SELECTIVELY PRECHARGING COLUMN LINES OF A MEMORY and U.S. Pat. No. 4,513,372, issued Apr. 23, 1985 to Ziegler et al, entitled UNIVERSAL MEMORY.
"A 32b VLSI System", Joseph W. Beyers, et al, 1982, Digest of Technical Papers, 1982, IEEE International Solid-State Circuits Conference, pages 128-129, mentions that a 128 Kb RAM is pipelined.